1. Field of the Invention
This invention relates generally to improvements in recording and information processing methods and apparatus and a recording medium therefor and, more particularly, to a new and improved recording medium, recording and information processing systems facilitating efficient and high speed processing at reduced cost.
2. Description of the Related Art
Recently, television game machines for home use or personal computers which effect picture drawing processing at a high speed, to allow a user to enjoy a game or the like, have become less expensive and have spread to a large number of homes.
In order to produce computer graphics (CG) or to develop software which uses the computer graphics, a graphic computer which effects picture drawing processing at a higher speed is used.
Such television game machines for home use, personal computers and graphic computers as described above typically include a picture drawing apparatus composed of a memory, a CPU (central processing unit) and other operation circuits. In the picture drawing apparatus, image data to be displayed on a display section of a television receiver or a display unit for exclusive use, that is, display data, are produced by the CPU, and the data thus produced are outputted to a frame buffer provided for holding values for pixels of the display section, so that high speed picture drawing processing is effected by the picture drawing circuit for exclusive use.
The CPU of the picture drawing apparatus effects geometry processing such as coordinate conversion, clipping and light source calculation to produce picture drawing commands for drawing a graphic form of a three-dimensional solid object in the form of a combination of basic plane figures (polygons) having such shapes as triangles or quadrangles and supplies the picture drawing commands to the picture drawing circuit.
The picture drawing circuit calculates values of pixels constructing the polygons from color data of the apexes of the polygons and Z values indicating positions of the polygons in the depthwise direction in the three-dimensional space displayed two-dimensionally on the predetermined display section, in accordance with the picture drawing commands received from the CPU, and then writes the values into the frame buffer (rendering processing) and draws a picture of the polygons.
Such a picture drawing circuit as described above is directly coupled to the CPU by a bus for exclusive use to prevent otherwise possible concentration of a load (data transmitted and received via a bus) on a different bus used commonly together with a different circuit (for example, a recording apparatus or a memory which holds data). It is to be noted that, when picture drawing processing is to be performed, for example, at a speed of approximately 15 MPolygon/sec (rendering processing of 15 10.sup.6 polygons is performed for one second) making use of the different bus used commonly together with the different circuit, the amount of data which are communicated along the bus used commonly together with the different circuit comes up to 100 MB/sec to 200 MB/sec (100 to 200 megabytes per second). Accordingly, a bus of a large capacity is required for the commonly used bus.
The data outputted from the CPU are stored once into a FIFO (first-in first-out) buffer interposed between the CPU and the picture drawing circuit and are supplied in the recorded order to the picture drawing circuit. The FIFO buffer successively stores therein and supplies the stored data to the picture drawing circuit such that, when the supplying rate of data by the CPU is temporarily higher than the processing speed of the picture drawing circuit, the stored amount of data thereof gradually increases, but the stored amount of data thereof gradually decreases when the supplying rate of data by the CPU is lower than the processing speed of the picture drawing circuit. In this manner, the FIFO buffer absorbs an imbalance between the data supplying rate of the CPU and the processing speed of the picture drawing circuit.
However, when the data supplying rate of the CPU exceeds the processing speed of the picture drawing circuit very much, or when a condition wherein the data supplying rate of the CPU is higher than the processing speed of the picture drawing circuit continues for a long period of time due to load conditions to the CPU and the picture drawing circuit, non-processed data are gradually accumulated in the FIFO buffer. Then, when the amount of such non-processed data exceeds the capacity of the FIFO buffer, matching of data is lost and, consequently, operation of the CPU and the picture drawing circuit stops. Therefore, such picture drawing apparatus has a disadvantage in that it is difficult to effect processing efficiently.
Another disadvantage of the picture drawing apparatus is that, in order to effect picture drawing processing at a high speed, as the amount of data to be processed for picture drawing increases, the capacity of the memory and the capacity of the recording medium required increase and, accordingly, it is difficult to achieve lower in cost.
In addition, the aforedescribed picture drawing apparatus suffers from the further disadvantage that, as the amount of data to be processed increases, the time required to read out data from the recording medium or the memory increases and, consequently, it is difficult to achieve a high processing speed.
Accordingly, these has been a long existing need for a new and improved recording medium and recording and information processing systems facilitating efficient and high speed processing at reduced cost. The present invention clearly fulfills these needs.